module uart_debug (
    input clk,
    input resetn,
    output reg reset_out,

    input uart_rx,
    output uart_tx,

    output reg [5:0]reg_addr,
    input [31:0] data,
    output reg reg_we
);
parameter CLK_FREQ=5000000;	//系统时钟频率
parameter UART_BPS=9600;		//波特率

wire [7:0] uart_rdata;
reg [7:0] uart_wdata;
reg uart_start;
wire uart_rxdone;
wire uart_txdone;
uart_recv
#(
	.CLK_FREQ	(CLK_FREQ),
	.UART_BPS	(UART_BPS)
)
u_uart_recv(
	.clk			(clk),
	.rst_n		(resetn),
	
	.uart_rxd	(uart_rx),
	.uart_data	(uart_rdata),
	.uart_done	(uart_rxdone)
);
uart_txd
#(
	.CLK_FREQ	(CLK_FREQ),
	.UART_BPS	(UART_BPS)
)
u_uart_txd(
	.clk			(clk),
	.rst_n		(resetn),

	.uart_txd	(uart_tx),
	.uart_en		(uart_start),

	.uart_data	(uart_wdata),
    .uart_tx_done (uart_txdone)
	);
reg uart_rxdone_r0;
wire uart_rxdone_pos;
always @(posedge clk) begin
    uart_rxdone_r0 <= uart_rxdone;
end
assign uart_rxdone_pos = uart_rxdone &(~uart_rxdone_r0);

reg [1:0] uart_state;
reg [3:0] uart_cnt;
reg uart_send_state;
parameter uart_send = 1'b0;
parameter uart_tx_wait = 1'b1;

parameter uart_idle = 2'b00;
parameter uart_parse = 2'b01;
parameter uart_work = 2'b10;
reg [7:0] control;
always@(posedge clk or negedge resetn) begin
    if(!resetn) begin
        reset_out <= 1'b0;
        uart_wdata <= 8'h0;
        uart_state <= uart_idle;
        uart_cnt <= 4'h0;
        uart_start <= 1'b0;
        uart_send_state <= uart_send;
    end
    else begin
        case(uart_state)
        uart_idle:begin
            reset_out <= 1'b1;
            uart_cnt <= 4'h0;
            uart_start <= 1'b0;
            if(uart_rxdone_pos) begin
                
                control <= uart_rdata;//
                uart_state <= uart_parse;
            end
        end
        uart_parse:begin
            case(control)
            8'hfe:begin
                uart_wdata <= 8'hfe;
                uart_start <= 1'b1;
                reset_out <= 1'b0;
                uart_cnt <= uart_cnt + 1'b1;
                if(uart_cnt == 4'h4) begin
                    uart_state <= uart_idle;
                end
                else begin
                    uart_state <= uart_state;
                end
            end
            default:uart_state <= uart_idle;
            endcase
        end
        uart_work:begin
            
            
        end
        endcase
    end
end    

endmodule